The invention relates to a return-to-zero transmitter.
Referring to FIG. 1, quite often it is desirable for digital circuits, such as circuits 10 and 12, to communicate with each other. For example, the circuit 10 might transmit digital bits to the circuit 12 over a communication line 14. The circuits 10 and 12 might be directly connected to the communication line 14. However, to minimize the occurrences of ground loops and DC mismatches between the two circuits 10 and 12, DC blocking elements, such as transformers or capacitors, might be used.
For example, a capacitor 16 may be used to isolate DC bias voltages of the circuits 10 and 12 from each other. However, in doing so, the capacitor 16 filters out the average, or DC component, of the stream of bits that is transmitted across the communication line 14. As a result, if the circuit 10 furnishes bits of data to the line 14, for example, the circuit 12 may encounter difficulties in recovering the bits because the logic one and logic zero threshold voltages of the bits may not be constant due to the filtering. Thus, because the threshold voltages are not constant, distinguishing logic one bits from logic zero bits may present difficulties.
Furthermore, relatively large and expensive high voltage capacitors (e.g., 100 picofarads or more) might be needed to decouple the line 14 from the circuits 10 and 12. Otherwise, without these large capacitors, the data might be undesirably attenuated.
To avoid these difficulties, the circuit 10 may encode the bits via a return-to-zero (RZ) encoding scheme so that the quiescent DC component of the encoded bit stream remains constant. Referring also to FIG. 2, when RZ encoding is used, each logic one bit 27 is encoded into a pair of pulses: a positive going RZ pulse 24 and a negative going RZ pulse 26. The two RZ pulses 24 and 26 are complementary so that each pair of RZ pulses does not disturb the DC level of the encoded bit stream. As a result, constant threshold voltage levels may be used to detect the positive 24 and negative 26 going RZ pulses and thus, decode the bits.
As compared to bits of unencoded data, RZ pulses have a relatively high frequency content. As a result, smaller and less expensive capacitors may be used to decouple the two circuits 10 and 12 from the line 14. Furthermore, due to the high frequency content of the RZ pulses, data may be transferred at a higher rate across the line 14.
Both circuits 10 and 12 might have an RZ transmitter and receiver pair to communicate with the line 14. For example, an RZ transmitter 20 (see FIG. 1) of the circuit 10 encodes a positively sloped edge 27a of the bit 27 into the positive going RZ pulse 24 and encodes a negatively sloped edge 27b of the bit 27 into the negative going RZ pulse 26. An RZ receiver 22 of the circuit 12 receives and decodes the RZ pulses 24 and 26 to reconstruct the bit 27.
Referring to FIG. 3, the RZ transmitter may be formed from, for example, a resistor-capacitor (RC) high pass filter circuit 30. However, a potential difficulty with this arrangement is that the magnitude of the RZ pulses which are generated by the circuit 30 (at its output terminal 32) may depend on the level, or magnitude, of the digital signal (called V.sub.I) that is present at an input terminal 31 of the circuit 30. Also, the response time of the circuit 30 may be decreased due to, for example, parasitic impedances (a pad capacitance, for example) present at the output terminal 32.
Thus, there is a continuing need for an RZ transmitter that is less sensitive to input voltage levels and/or parasitic impedances of such a system.